The present invention relates to a computer system and, more particularly, to a computer system which is improved to connect two buses to each other through a serial transmission path.
Recently, various portable, battery-driven, notebook type personal computers (to be referred to as notebook PCs hereinafter) have been developed. Some notebook PCs are designed to be attached to expansion units to expand the functions as needed. To allow a notebook PC body to effectively use the resources of an expansion unit, it is important to connect the bus of the notebook PC body to the bus in the expansion unit. With this bus connection, devices on the bus in the expansion unit can be handled in the same manner as devices in the notebook PC body.
In many personal computers, PCI (Peripheral Component Interface) buses are used. Bus connection between a notebook PC body and an expansion unit is generally performed by physically connecting PCI buses on the notebook PC body side to expansion unit side through docking connectors, each having many pins corresponding to the number of signal lines of each PCI bus, prepared on the notebook PC body side and expansion unit side.
According to this arrangement, however, a physically large area is required to mount a docking connector. This causes a disadvantage in attaining reductions in the size and profile of the notebook PC body. In addition, the connector mounting position on the notebook PC body side needs to match that on the expansion unit side. This imposes limitations on a physical housing structure in production development.
A technique of connecting a PC body to an expansion unit through a cable by using a standard parallel port of the PC body is disclosed in U.S. Pat. Nos. 5,457,785, 5,579,489, and 5,619,659. According to this technique, an ISA (Industry Standard Architecture) bus is formed in the expansion unit connected to the PC body through the cable via the standard parallel port of the PC body, and the ISA bus in the expansion unit is operated in the same manner as the ISA bus in the PC body by using a circuit for translating the signal state of the ISA bus in the PC body.
U.S. Pat. No. 5,822,571 also discloses an arrangement in which a PCI bus is extended from a PC body to another housing by connecting a PCI bus on the primary side to a PCI bus on the secondary side through a flat cable, and a clock synchronization method of coping with a transmission delay in a cable.
According to these conventional cable connection methods, however, since data are transferred in parallel through a cable, the cable is provided with many signal lines. For this reason, the following problems arise:
1) The cable becomes thick, difficult to handle, and expensive.
2) The number of pins of connectors for cable connection increases, and hence the cost of each connector increases. This also interferes with a reduction in size.
In general, a PCI-PCI bridge is used to connect a plurality of PCI buses on a system board. The PCI-PCI bridge is an LSI for bidirectionally connecting a primary PCI bus to a secondary PCI bus. This bridge allows a device on the primary PCI bus to access a device on the secondary PCI bus, and vice versa. Such PCI-PCI bridges may be provided at two ends of a cable to connect the PCI bus of the notebook PC body to the PCI bus in the expansion unit. In this arrangement, however, the cable portion also serves as a PCI bus (to which an individual bus number is assigned) according to the PCI specifications, and hence a total of three PCI buses must be managed from the viewpoint of software. Since no PCI device is connected to the cable connecting the notebook PC body to the expansion unit, assigning a bus number to the cable leads to wasting resources. In addition, this becomes a factor that complicates resource management by software.
The present invention has been made in consideration of the above situation, and has as its object to provide a computer system which can connect a computer body to an expansion unit through a cable with a smaller number of signal lines, realizes a new bus connection scheme that prevents resources from being wastefully assigned to the cable, and is excellent in function expandability and flexibility of the housing structure.
In order to achieve the above object, a computer system of the present invention is characterized by comprising first and second buses respectively constituted by multiple-bit-width parallel transmission paths; a first controller connected to the first bus; a second controller connected to the second bus; and a serial transmission path interposed between the first and second controllers; wherein the first and second controllers exchange a command, address, and data of a transaction from one of the first and second buses to the other bus by serial transfer through the serial transmission path, and the first and second controllers logically constitute one unit.
In this computer system, the bridge unit for connecting the first and second buses to each other is divided into two physically isolated controllers, and two controllers are connected to each other through a serial transmission path. A command, address, and data required for transfer of a transaction between the buses are exchanged between two controllers by serial transfer through this serial transmission path. This allows a transaction on one bus to be reproduced on the other bus. If, therefore, two controllers are separately provided in a computer body in which the first bus is provided and an expansion unit in which the second bus is provided, and a serial transmission path between these controllers is implemented by a cable, the computer body can be connected to the expansion unit through a cable with a smaller number of signal lines. In addition, the first and second controllers logically constitute one single bridge unit. Therefore, the serial transmission path is just a local internal wiring inside the bridge unit and is not recognized by software. This means that no unnecessary resource is assigned to the serial transmission path.
Furthermore, since the logically single controller is physically divided into two controllers, special design is required more or less. Many of configuration registers in which operation environments are to be set are preferably implemented in two controllers, and identical pieces of environmental setting information are preferably set in these registers. If configuration registers are implemented in only one of two controllers, the other controller must read the configuration registers in one controller through the serial transmission path whenever the information stored in these registers becomes necessary. This causes degradation in system performance. If configuration registers are separately implemented in two controllers, as needed, each controller can operate in accordance with the environmental setting information set in the corresponding configuration registers. This makes it possible to perform high-speed operation.
Since serial transfer through the serial transmission path requires a clock signal faster than a bus clock signal, a means for improving noise resistance is required. For this reason, a differential signal line pair in which a transformer is inserted is preferably used as a serial transmission path. With the insertion of the transformer, transfer for the DC components of a signal can be prevented, and hence noise resistance to common mode noise such as static electricity can be improved.
If a differential signal line pair in which a transformer is inserted is to be used, it is important to ensure a satisfactory DC balance with respect to a transmission signal in consideration of the characteristics of the transformer. This is because magnetic saturation or excitation of the transformer and a shift in the offset level of a signal on the secondary side of the transformer must be prevented. For this reason, serial transfer is preferably performed by using a scheme of converting each binary data constituting serial data into ternary data including the first state in which a current flows in the transformer in a positive direction, the second state in which a current flows in the transformer in a negative direction, and the third state in which no current flows in the transformer, and transmitting the ternary data. For example, a satisfactory DC balance can be ensured by, for example, control operation of outputting ternary data upon alternately switching the first and second states every time the value of binary data changes, and outputting data with the third state when the value of binary data remains unchanged. For another example, the satisfactory DC balance can also be ensured by control operation of outputting data with the third state when the value of binary data is xe2x80x9c0xe2x80x9d, and outputting data while alternately switching the first and third states when the value of binary data is xe2x80x9c1xe2x80x9d.
An nBmB scheme of transmitting information required for transaction transfer by encoding the information into m-bit (m greater than n) code sequences in units of n-bit information words can be used instead of using the above ternary scheme. A satisfactory DC balance can be ensured by converting information words into code sequences with ratios for the numbers of xe2x80x9c1sxe2x80x9d to the numbers of xe2x80x9c0sxe2x80x9d are equal, and transmitting the code sequences.
Each of the first and second controllers preferably comprises bus interface means which operates in synchronous with the same first clock signal as that used by a device on a corresponding one of the first and second buses so as to exchange a transaction with the corresponding bus, and serial transfer means which operates in synchronous with a second clock signal asynchronous to the first clock signal so as to execute serial transfer through the serial transmission path.
Since the first clock signal is a bus clock signal, its frequency needs to be set to a standard value determined by bus specifications. In addition, a bus clock signal may be stopped for power saving control. By operating the bus interface means and serial transfer means asynchronously, serial transfer performance can be arbitrarily determined without being influenced by the frequency of the first clock signal, the state of the bus, and the like.
The bus interface means of the first and second controllers are preferably operated asynchronously. By setting asynchronous clock signals at two ends of the serial transmission path in this manner, accurate transaction transfer can be performed regardless of the transmission delay due to serial transfer.
The serial transmission path is characterized by comprising a full duplex channel including at least one pair of unidirectional serial transmission paths whose signal transmission directions are opposite to each other, and each of the unidirectional serial transmission paths includes a serial data line for serially transferring of the command, address, and data, and a clock signal line for transferring a corresponding clock signal. With this arrangement, a full duplex channel can be realized by using a serial transmission path. In addition, sufficiently high-speed serial transfer can be realized by providing a clock signal line independently of a serial data line as compared with the case wherein clock information is embedded in data.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.